Another advantage of pulse-triggered FFs is that they allow time borrowing across cycle boundaries and feature zero or even negative setup time. It can thus provide higher toggle rate than the conventional FF can and is found useful in high speed applications. The circuit complexity of a pulse-triggered FF is thus greatly simplified since only one latch, as opposed to two latches in master-slave configuration, is needed. Since the pulses are generated on the transition edges of the clock signal and very narrow in pulse width, the latch acts like an edge-triggered FF.
#EDGE TRIGGERED FLIP FLOP SYMBOL GENERATOR#
A pulse-triggered FF consists of a pulse generator (also called transition detector) for strobe signals and a latch for data storage. To reduce the circuit complexity, pulse-triggered FFs have been considered as a popular alternative to the conventional master-slave-based FF these days. FFs thus contribute a significant portion of gate count to the overall system design. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file and shift register. Introductionįlip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. Postlayout simulations in TSMC 1P6M 0.18 μm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design.
It supports both single-edge- and double-edge-triggered operations subject to a mode select control. A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper.
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